Because of the complicated and highly refined nature of semiconductors fabrication processes, it is imperative that various parameters be carefully controlled to insure that the completed device complies with all technical specifications. To that end, post-fabrication testing on selected bar or die parts of a silicon wafer or slice is routinely conducted to ascertain that various circuit parameters meet both published specifications and process specifications. Generally, various dies of a silicon wafer include test transistors fabricated by the same process as the functional circuits on the dies of the silicon wafer. During testing, a test fixture makes electrical contact directly to the test transistors and applies voltages thereto to determine characteristics, such as the threshold voltage V.sub.t and the conductance K' of the test transistors. The values of these characteristics are indications of fabrication process parameters.
Another approach taken to ascertain fabrication parameters is to design a test circuit, or transistor, into every die on the wafer. The test circuit is wholly independent of the functional circuit on the die, and is accessible by test equipment only through microcontacts on the die. Testing of the test circuit can only be accomplished before the die is encapsulated into a package, such as a dual in-line package. The test circuit is not connected to the input/output pins of the packaged device and thus cannot be accessed from such pins.
The post-packaging examination of integrated circuits is an important aid in gathering information relating to process parameters. For example, when integrated circuits are returned to the manufacturer, process parameters derived from the testing of the test circuit may be correlated to the mode of failure. However, in order to gain access to the test circuit, the encapsulation or package of the integrated circuit must be removed in order to gain access to the test circuit microcontacts. The removal of the encapsulant must be carefully done so that the integrated circuit itself is not damaged, and valuable information thereby lost.
From the foregoing, it may be seen that a need has arisen for a packaged integrated circuit in which the test circuitry can be accessed from the Input/Output (I/O) pins of the device, without the presence of the test circuitry affecting the normal operation of the device.